hi gdhp
the switching threshold voltage of an inv is determined by the kn/kp of the nmos and pmos FET. when out is 1, I2 is off and I4 is on and parallel to I5; when out is 0, I4 is off and I2 is on and parallel to I3. Values of kn/kp in these 2 condition are different, so the trigger voltages.
refer to cmos schmitt trigger section of rabaey's 'digital integrated circuits' for detail.
to reduce the delay, make the W/L of transistors larger.
try to reduce gate areas of fets in L2.
It may be a heavy cap load of the preceding inverter.
again refer to rabaey's book for optimizing cascaded inverters
gdhp said:
hi vale
the W/L is 2/0.34 adn 6/0.34 of L2 inverter.
In my circuit, the delay is about 2-4ns, it is too large to my requiment.
But if i increase the W/L, the current is also large, it is not my wish.
so i am puzzled!
Added after 22 minutes:
i think the wL of L2 is is too large!thank you vale!