Design op amp in standard CMOS with High Voltage Protectio

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The CMOS process I am using has maximum 6V supply voltage, I'm going to design an op amp using this process plus high voltage protection circuit (18V). Can anyone give me some idea. Thanks a lot!
 

Re: How to design high Voltage op amp in standard CMOS proce

Using de overdrive rules u can design..
 

Re: How to design high Voltage op amp in standard CMOS proce

Check if the process has high voltage NMOS devices where the drain is made using a N-well. This is one way to obtain a high-voltage NMOS in any CMOS process. AMS C35 for example has this device in the design kit.
 

Re: Design op amp in standard CMOS with High Voltage Prote

Here's an intersting paper showing these kind of devices, and mismatch modeling also.
 

It is not good way to design such 18V circuit in a process without HV device.
 

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