Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: How to design high Voltage op amp in standard CMOS proce
Check if the process has high voltage NMOS devices where the drain is made using a N-well. This is one way to obtain a high-voltage NMOS in any CMOS process. AMS C35 for example has this device in the design kit.