design of a ddr sdram controller

tinytseng · Jul 21, 2007

I will do a ddr sdram controller design,but i dnt know how to capture the data at both pos and neg edge of system clock(because it is not recommanded to use both pos and neg clk in verilog)

could anybody who has this experience help me?

rjainv · Jul 21, 2007

you can have another clock running at double the freq of your system clock capture the data and do DDR to SDR conversion.

btw, for incoming data, you have to use dqs to capture data.

what I said is true for outbound, let higher freq clk do SDR to DDR conversion.

hawk_chenbo · Jul 30, 2007

Say Data from internal bus is 32-bit width, Data[15:0] can output when output clock is high and Data[31:0] when clock is low.

nemolee · Oct 2, 2007

As I know, there are two methods to capture the input data.
One is capture data by phase-shifted clock.
The other is delayed DQS.
I never try these approaches.
Does anyone try these methods?
Please share your experience to everyone.
Thank you.

design of a ddr sdram controller

tinytseng

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rjainv

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hawk_chenbo

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nemolee

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design of a ddr sdram controller

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