Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

design of a ddr sdram controller

Status
Not open for further replies.

tinytseng

Newbie level 6
Joined
Aug 8, 2006
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,349
I will do a ddr sdram controller design,but i dnt know how to capture the data at both pos and neg edge of system clock(because it is not recommanded to use both pos and neg clk in verilog)

could anybody who has this experience help me?
 

rjainv

Full Member level 2
Joined
Feb 18, 2007
Messages
140
Helped
18
Reputation
36
Reaction score
4
Trophy points
1,298
Location
Bangalore, India
Activity points
2,066
you can have another clock running at double the freq of your system clock capture the data and do DDR to SDR conversion.


btw, for incoming data, you have to use dqs to capture data.

what I said is true for outbound, let higher freq clk do SDR to DDR conversion.
 

hawk_chenbo

Member level 2
Joined
Sep 28, 2004
Messages
43
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Activity points
254
Say Data from internal bus is 32-bit width, Data[15:0] can output when output clock is high and Data[31:0] when clock is low.
 

nemolee

Full Member level 3
Joined
Dec 28, 2004
Messages
155
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,298
Activity points
1,460
As I know, there are two methods to capture the input data.
One is capture data by phase-shifted clock.
The other is delayed DQS.
I never try these approaches.
Does anyone try these methods?
Please share your experience to everyone.
Thank you.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top