design not gate by using and gate

[naaj_ila]

hai all
i was asked this question ..in Interview..
can any body solve this??

 

[A.Anand Srinivasan]

OR, AND and OR are basic gates and none of them can be used individually to realise the other... they can be used in a combination of 2 to realise the third....

 

[gliss]

Are you sure the question wasn't to use a NAND gate to implement NOT?

A -----|---\
       |    |>----- ~A
A -----|---/

You see, tie the input signal to both inputs of a 2 input NAND gate and you get NOT.

 

[pintuinvlsi]

NOT and AND or OR gates are universal gates, Either combination of AND/NOT or OR/NOT can be used to realize any gate and so NAND and NOR are also can be used to implement any digital circuit.

 

[naaj_ila]

hai guys

In interview i said its impossible
he said it is possible >>>


i thought like this

depending on the and gate delay it depends
Example::if and gate delay is 5ns(say)then
apply logic 1 as one input
apply A as another input of period 10ns(synchronous) waveform
we get the output as Abar..

practically it maynot possible

me and my friends discussed a lot and had came to this answers...
many of them wont agree this...but i think this may be the possibility...

any more suggestions

 

[pintuinvlsi]

But Output will be same as input A, only shifted by 5 ns. If input waveform is not symetric then it won't be inverted one.

 

[sizzlers]

hello,

it is not possible.the output is a only,but it is delayed by 5ns.

 

[A.Anand Srinivasan]

it is not possible... actually if you implement it as you said then the output is supposed to be inverted no matter what and as long as the input stays in a particular logic level....

 

[naaj_ila]

just check this waveforms.

i know many of them wont agree this..

what should i say to anybody when they ask this question

 

[kpsai26779]

Hi naaj_ila,

clearly observe your wave form, your AND gate is simply giving delayed o/p only. For better understanding just vary ON and OFF periods of A and observe the change.

interviewer may be testing your confidence

 

[A.Anand Srinivasan]

well talkin in terms of propagation delay... you are just sending delayed versions of the output and this is just a buffer with a delay not a NOT gate...