darkk
Member level 3
scl cml
Hi, folks
I have a simple question about the design issue of CML/SCL, which is short for source coupled logic. Especially, I'm intrested in the stacked SCL circuits such as flip-flop or MUX.
For example, in the classical CML flip-flop based on bipolar transistors, the level shift for the clock signal is necessary to secure the transistors on the bottom level to operate in the right working region. As shown in the first picture below, the level shift function is implemented by the emitter follower at the left.
But for the source coupled logic flip-flop based on CMOS transistors, the level shift is rarely addressed by any reference. It seems that someone did use source follower to implement the level shift as in the bipolar process. Also someone just ignored it at all. It means data signal to top level transistors have the same common mode voltage as the clock signal to bottom level transistors. As shown in the second picture below, in/inb and clock/clockb have the low and high input voltage as Vdd-Vswing and Vdd.
So it really makes me confused at this point. What do you guys think about that? Any inputs will be appreciated much.
Hi, folks
I have a simple question about the design issue of CML/SCL, which is short for source coupled logic. Especially, I'm intrested in the stacked SCL circuits such as flip-flop or MUX.
For example, in the classical CML flip-flop based on bipolar transistors, the level shift for the clock signal is necessary to secure the transistors on the bottom level to operate in the right working region. As shown in the first picture below, the level shift function is implemented by the emitter follower at the left.
But for the source coupled logic flip-flop based on CMOS transistors, the level shift is rarely addressed by any reference. It seems that someone did use source follower to implement the level shift as in the bipolar process. Also someone just ignored it at all. It means data signal to top level transistors have the same common mode voltage as the clock signal to bottom level transistors. As shown in the second picture below, in/inb and clock/clockb have the low and high input voltage as Vdd-Vswing and Vdd.
So it really makes me confused at this point. What do you guys think about that? Any inputs will be appreciated much.