Hi, analysis should have provided some feedback on the problem:
For example:
Warning: In design ‘myDesign’, there are sequential cells not connected to any load. (OPT-109)
Information: Use the ‘check_design’ command for more information about warnings. (LINT-99)
during compile time it was giving this warning. If i issue check_design after compile it does not give anything. When i refer help it says that we need to reload the design again and issue check_design.
after compile , how to reload and issue check_design
during compile time it was giving this warning. If i issue check_design after compile it does not give anything. When i refer help it says that we need to reload the design again and issue check_design.
after compile , how to reload and issue check_design
Hi, the warning you received may have pertained to unused memory elements (flops where the Q/QB are floating). The synthesis tool will remove these elements unless explicitly told not to. You need to run check_design earlier (before compiling) in order to get more detail; try running right before uniquify.
The reason you do not get the warning after compile is that the tool probably remove the offending cells.
Please be sure to understand completely any warnings that come from the synthesis tool. The warnings are telling you that the tool is going to make a decision and the decision may or may not be your intention. It is possible to synthesize gates whose function will not compare to the RTL simulation results; it is not the synthesis tool's problem, it is related to the RTL that comes into the tool.