Re: Design Compiler Warning (OPT-150)(OPT-314) break a timing loop,anyone help me?
Looking at the circuit, I suspect the FFs are outputting X for both Qref and Qfb starting from time 0, as the NAND gate producing PDrst has X inputs it produces an X output, which in turn causes the FF models to ignore the fref and ffb clocks and produce Xs on the FF outputs again.
The original RTL simulation works because the if (!reset) in the FF code will be false as reset is X which will always mean the else is taken so Q gets assigned the D input. The model for the gate level netlist doesn't behave this way as it likely checks for X's on all the inputs and assigns Q <= 1'bx;
X's on resets can result in strange behaviors vs gate level code.
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Realistically the gate level netlist will likely work as the FFs will power up either 1 or 0 and the circuit will have a valid logic input to the !RST input. The X is a simulation artifact that results in the simulation misbehavior that won't occur in the real world.
I'd suggest adding an initial statement to the test bench and assign both FF outputs with 0, the 0's will be overridden once the first ffb and fref arrive.