Thanks for your comments in advance!As for the DC-T, should floorplaning be performed in prior to Logic Synthesis?
How floorplaning might be performed in prior to Logic Synthesis if the cells area is still unknown?
What is "topolofical view"? As you wrote, firstly we should run a "dirty" Logic Synthesis for just having an idea about the gates count and only then pass the Netlist to Floorplaning. Correct? So, for the first "dirty" synthesis the DC-T doesn't have any floorplaning info, correct? Can DC-T constrain gates count according to floorplaning info?normally, in topolofical view, it will estimate a "real" wire length, based on the topology, so the WLM is not used.