Design Compiler Topological Flow

[ivlsi]

HI ALL,

Could someone share his/her knowledge on Design Compiler Topological ?

What's the difference with a regular Design Compiler flow?

THANK YOU!

 

[rca]

The basic idea is the synthesis tool will know the placement of macro, pads, and could estimated more precisely the wire length and sizing the cells appropriately.

 

[ivlsi]

Will the info (cells placement) then be passed to PNR tools? What format?

As for DC-T, should floorplaning be performed in prior to Logic Synthesis? What format should it be passed to DC-T?

How floorplaning might be performed in prior to Logic Synthesis if the cells area is still unknown?

Wld floorplaning take 20% for future routing?

Thank you!

 

[rca]

Def file could be used

 

[ivlsi]

okay, thank you... But I still have some questions not answered... Here they are:

As for the DC-T, should floorplaning be performed in prior to Logic Synthesis?

How floorplaning might be performed in prior to Logic Synthesis if the cells area is still unknown?

Thanks for your comments in advance!

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As for the DEF, it's Cadence's format. Synopsys usually uses MilkyWay... Am I wrong?

 

[rca]

so first synthesis to have the overall area
made your floorplan
then rerun more precise synthesis with the floorplan information.,
you're right¨!

 

[ivlsi]

ok, for the first run before the floorplaning, should any WLM be used? Should it be Zero-WLM? Any timing violations might be accepted?

 

[rca]

normally, in topolofical view, it will estimate a "real" wire length, based on the topology, so the WLM is not used.

 

[ivlsi]

normally, in topolofical view, it will estimate a "real" wire length, based on the topology, so the WLM is not used.

What is "topolofical view"? As you wrote, firstly we should run a "dirty" Logic Synthesis for just having an idea about the gates count and only then pass the Netlist to Floorplaning. Correct? So, for the first "dirty" synthesis the DC-T doesn't have any floorplaning info, correct? Can DC-T constrain gates count according to floorplaning info?

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What Output files from DC-T?
My guess is:
1) Netlist (*.v, *.db)
2) Timing constraints (*.sdc)
3) DEF(?) Milkyway(?) files

Please help

 

[rca]

well during the first synthesis is to have a far-away std-cell area estimation, and you don't really care of this first area/timing.

As output of the topology flow, you should have the cell placement through DEF or directly the milkyway database.

 

[sharath666]

First of all, it is not tolpological flow;it is topographical flow.
Flow:
1.Run DC using a basic WLM and correct constraints to get a netlist.
2.Use this netlist to get a DEF.
3.Run DC-T again using this def, removing the WLM and with the same constraints.This run of DC-T will require Milkyway libraries as well apart from normal .db's.
4.This run will also realise a netlistddc & sdc.

 

[ivlsi]

What do include the Milkyway libraries?

 

[sharath666]

R u asking why do we include the milkyway libraries? That is because the DEF file uses cells from that library...