vyella1
Newbie level 6
Hello Forum,
I am working on RTL synthesis of an ECC Decoder(which has many sub modules) using design compiler, and I encountered a timing violation and the critical path is in sub module ABC. Accidentally I turned on a pipeline stage in different path (critical path and this path are not related at all) and it fixed the timing violation. Is it normal to see such synthesis behavior? I am trying to understand how it fixed the timing violation.
I am working on RTL synthesis of an ECC Decoder(which has many sub modules) using design compiler, and I encountered a timing violation and the critical path is in sub module ABC. Accidentally I turned on a pipeline stage in different path (critical path and this path are not related at all) and it fixed the timing violation. Is it normal to see such synthesis behavior? I am trying to understand how it fixed the timing violation.