Design Compiler synthesis error

Status
Not open for further replies.

ryodan_2004

Newbie level 3
Joined
Jul 5, 2008
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,307
I have a vhdl code, with constant values tied at the ports
e.g. m1 : port map mux ('0',a,b,c) ...

i've got errors because of the constants direct port assignments

Any additional script commands to remove this error ? TIA
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…