gstekboy
Member level 5
I coded 2 different MAC architecture in verilog and run in synopsys design compiler.
While compiling the design , I analysed the MAC architecture area, power and timing by checking and without checking ungroup option .
First MAC architecture
By using ungroup option in Design compiler , Area, power and timing(delay time) reports are less than that of grouped results.
Second MAC architecture
By using ungroup option in Design compiler , Area, power and timing(delay time) reports are more than that of grouped results.
Why these difference occurs?:bang::bang::bang:
While compiling the design , I analysed the MAC architecture area, power and timing by checking and without checking ungroup option .
First MAC architecture
By using ungroup option in Design compiler , Area, power and timing(delay time) reports are less than that of grouped results.
Second MAC architecture
By using ungroup option in Design compiler , Area, power and timing(delay time) reports are more than that of grouped results.
Why these difference occurs?:bang::bang::bang: