ammmmlol
Newbie level 4
Hi,
I tried to synthesize a 64-bit adder. It's pure combinational. When I set the virtual clk to 1GHz. The timing report is
And for 2GHz clock, the timing report is
They are both negative. But I think if Design Compiler uses the optimization method for 2GHz in 1GHz case, I can have a positive slack (0.9-0.62 = 0.28) for 1GHz case. It seems with proper optimization, my circuit should be able to run in 1GHz. Is this assumption valid? And if so, how do I tell DC to use the optimization method for 2GHz which it currently uses in 1GHz case.
I tried to synthesize a 64-bit adder. It's pure combinational. When I set the virtual clk to 1GHz. The timing report is
PHP:
clock vclk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
output external delay -0.10 0.90
data required time 0.90
-----------------------------------------------------------
data required time 0.90
data arrival time -0.92
-----------------------------------------------------------
slack (VIOLATED) -0.02
And for 2GHz clock, the timing report is
PHP:
clock vclk (rise edge) 0.50 0.50
clock network delay (ideal) 0.00 0.50
output external delay -0.10 0.40
data required time 0.40
-----------------------------------------------------------
data required time 0.40
data arrival time -0.62
-----------------------------------------------------------
slack (VIOLATED) -0.22
They are both negative. But I think if Design Compiler uses the optimization method for 2GHz in 1GHz case, I can have a positive slack (0.9-0.62 = 0.28) for 1GHz case. It seems with proper optimization, my circuit should be able to run in 1GHz. Is this assumption valid? And if so, how do I tell DC to use the optimization method for 2GHz which it currently uses in 1GHz case.