Here are my answer, hope it helps:
1. On synthesis, timing is 0 clock latency. So, it mean that timing result is all about your data path which represented for what logic your have.
In both cases of your results, you still see timing violations, it means your logic can not work with that speed in silicon or FPGA ideally. I dont know yet about your other margin or constraint.
Once you see timing violation on synthesis result, it meant that you have to do some analysis for data path logic, clock freq and constraints that you used. Or try another technology libraries.
If you only do gate level design preparation, and you have intention to do timing optimization on PnR step, you can ignore synthesis timing violation. But I seldom do that.
2. PnR need gate level design and, Yes, PnR tool has timing optimization engine, of-course PnR tool takes care clock and data path.
3. Yes. It is possible neighbour blocks still have margin for you. Or say, their data path can be optimized more.
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Be aware of area overhead once you use higher speed in synthesis.
And also, rerun the 2Ghz design with the constraint 1Ghz to see the timing met or not.
This can be useful sometimes.