meldron1X
Newbie level 3
Hello,
I'm using Synopsys Design Compiler for synthesis. Does anybody know how I can connect all ports of my gates when I'm writing out my netlist?
E.g.:
DC writes as netlist (verilog):
'DFF DF1 ( .D(n1), .C(clk), .RN(reset_n), .Q(n2));'
ignoring port QN which is not used.
But, I would like to have this port also in my final netlist, like this:
DFF DF1 ( .D(n1), .C(clk), .RN(reset_n), .Q(n2), .QN(dummy) );
Thank you for help/hints
I'm using Synopsys Design Compiler for synthesis. Does anybody know how I can connect all ports of my gates when I'm writing out my netlist?
E.g.:
DC writes as netlist (verilog):
'DFF DF1 ( .D(n1), .C(clk), .RN(reset_n), .Q(n2));'
ignoring port QN which is not used.
But, I would like to have this port also in my final netlist, like this:
DFF DF1 ( .D(n1), .C(clk), .RN(reset_n), .Q(n2), .QN(dummy) );
Thank you for help/hints