doesn't current source+cap act the same like RC? the bandwidth is severely limited, high frequency will be cut off.
let's say, u want to delay with small current, which translate to longer charge time for the cap, which translate to poor high frequency response.
if you have signal bandwidth much larger than the 3us(330KHz) delay, the only Analog way I can think of doing this is using a "Sample and Hold" Pipeline with switch capacitor technology. for each clock cycle, you "Sample" an input signal and "Pass" it to the next stage, exactly the same way as Digital FIFO, except that you don't need to do the A/D converting.