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Design a i/o port that meet -7~12V?

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fengluan

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in order to prevent Psub-nwell diode forward conduct when voltage is negetive , a iso-nmos is used. now the problem is whether two nmos may oxide rupture,
the process has BDVds>12V, but Tox is 150A, so Vgs<5V to avoid oxide rupture.

but for my schematic configuration, Vgs(Vgd) some time exceed 5V.
 

There is a doubt how can nmos operate when Vds=12V and BDVgd<5V simultaneously?
U have wrong opinion regarding safe operation regions of MOSs in ur process.
BDVgd can be higher than BDVgs for special device structures. Look in PDK docs or ask FAB about.
 

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