# design a digital circuit

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#### piano

##### Newbie level 5
can any design a digital circuit whose output comes in following fashion

0000 -> 1000 -> 1100 -> 1110 -> 1111 -> 0000 -> 1111 -> 0111 -> 0011 ->0001 -> 0000 -> 1111 -> 0000

plz give the verilog code also, if possible.

#### nand_gates

##### Advanced Member level 3
Here it goes along with the test bench!
Hope this helps!

Code:
module seq(clk, reset, seq_out);
input clk, reset;
output [3:0] seq_out;
reg [3:0] seqence, seqence_nx;
reg       flag, flag_r, flag_nx;
assign    seq_out = seqence ^ {4{flag_r}};
always @(posedge clk or posedge reset) begin
if (reset) begin
seqence <= 0;
flag <= 0;
end else begin
seqence <= seqence_nx;
flag <= flag_nx;
flag_r <= flag;
end
end
always @(/*AS*/flag or flag_r or seqence) begin
flag_nx = &seqence ^ flag;
if (flag == flag_r) begin
seqence_nx[0] = (~&seqence) & (&seqence[3:1]);
seqence_nx[1] = (~&seqence) & (&seqence[3:2]);
seqence_nx[2] = (~&seqence) & (seqence[3]   );
seqence_nx[3] = (~&seqence) | (~|seqence);
end else begin
seqence_nx = seqence;
end
end

endmodule // seq

module test();
reg                  clk;     // To seq of seq.v
reg                  reset;   // To seq of seq.v
wire [3:0]           seq_out; // From seq of seq.v

seq seq(
// Outputs
.seq_out                     (seq_out[3:0]),
// Inputs
.clk                         (clk),
.reset                       (reset));
initial begin
$monitor ($time,,"reset = %b seq = %b", reset, seq_out);
clk = 0; reset = 1;
#33 reset = 0;
#2000 \$finish;
end
always #5 clk = ~clk;
endmodule // test

#### piano

##### Newbie level 5
thanx nand for the codes.

if possible can anyone provide structural coding of sequence

#### laglead

##### Full Member level 5
using state machine

#### aslijia

##### Member level 2
use shift register and some DFF to store one bit control signal. I will give you the structual level code later.

Added after 2 hours 17 minutes:

if you don't want to use state mathine, you can use a Johnson counter and 12 DFFs, which is used to store the control signal.

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