design a 8 bit processor with the following specifications

[macgradywk]

Design a 8 bit processor with the following specifications1:
1. The processor has seven 8-bit registers A, B, C, D, E, H and L.
2. It connects with an external memory containing 32 8-bit words. The memory has a
tristate output with active low signals rd and wr.
3. It has instructions MOV, LDA, STA, ADD, SUB NOP and HLT. It can also add or
subtract data directly from memory.
4. The op-codes for the instructions are defined as follows. The registers A, B, C, D, H
and L are coded as 111, 000, 001, 010, 011, 100 and 101 respectively. The letter M
always refers to the contents of the memory address in the least significant 5 bits of
the L register2. The opcodes may then be described as follows:
01 d2d1d0 s2s1s0 : MOV r1, r2 (copy reg s2s1s0 to register d2d1d0)
01 110 s2s1s0 : MOV M, r (copy reg s2s1s0 to memory)
01 d2d1d0 110 : MOV r, M (copy memory contents to register d2d1d0)
01 110 110 : HLT (halt the processor)
10 000 s2s1s0 : ADD r (add reg s2s1s0 to register A)
10 000 110 : ADD M (add memory contents to register A)
10 010 s2s1s0 : SUB r (subtract reg s2s1s0 from reg A)
10 010 110 : SUB M (subtract memory contents from register A)
11 1a4a3 a2a1a0 : STA addr (store A to memory address a4a3a2a1a0)
00 1a4a3 a2a1a0 : LDA addr (load A from address a4a3a2a1a0)
00 000 000 : NOP (do not do anything)

how to do that?

 

[HTA]

Hi,

the best it to look to the principle architecture of an existing 8-Bit microcontroller and then design each element you need according to the requirements. Here you find the the architeture of a Z80: https://en.wikipedia.org/w/index.php?title=File:Z80_arch.svg&page=1

Enjoy your design work!

 

[TrickyDicky]

This sounds very similar to my final year project.
Heres what I did:
wrote a load of notes in lectures, learned and HDL and coded the project with a little help from friends and tutor.

So instead of just asking us to do the work, get started yourself, and come back when you have a specific problem.

 

[macgradywk]

I do not know what the opcodes means.

for example, 111 stands for A, but there is no 111 in the code, how can it relate to A?

01 d2d1d0 s2s1s0 : MOV r1, r2 (copy reg s2s1s0 to register d2d1d0)
01 110 s2s1s0 : MOV M, r (copy reg s2s1s0 to memory)
01 d2d1d0 110 : MOV r, M (copy memory contents to register d2d1d0)
01 110 110 : HLT (halt the processor)
10 000 s2s1s0 : ADD r (add reg s2s1s0 to register A)
10 000 110 : ADD M (add memory contents to register A)
10 010 s2s1s0 : SUB r (subtract reg s2s1s0 from reg A)
10 010 110 : SUB M (subtract memory contents from register A)
11 1a4a3 a2a1a0 : STA addr (store A to memory address a4a3a2a1a0)
00 1a4a3 a2a1a0 : LDA addr (load A from address a4a3a2a1a0)
00 000 000 : NOP (do not do anything)

 

[HTA]

If A is the accumulator, the OP-Code STA or LDA defines the address of A. So no other coding needed.

Enjoy your design work!

 

[ads_ee]

4. The op-codes for the instructions are defined as follows. The registers A, B, C, D, H
and L are coded as 111, 000, 001, 010, 011, 100 and 101 respectively.

I think there is something wrong with the posting as there are 7 coded registers and only 6 names for those registers?

If this is the coding then there is either a missing register or the coding should have been A = 000, B = 001, ... , L = 101. With this coding the instructions like:

10 000 110 : ADD M (add memory contents to register A)

actually make sense (where M is coded as 110 and specifies using the L register [5:0], indirect addressing).

Regards,
-alan

 

[macgradywk]

I think you are right, but there is another problem:
10 010 s2s1s0 : SUB r (subtract reg s2s1s0 from reg A)
10 010 110 : SUB M (subtract memory contents from register A)
For 010 is C as you said, the two operation above should be add s2s1s0 or M to C, how can it be a subtraction?
And what are the following mean?
11 1a4a3 a2a1a0 : STA addr (store A to memory address a4a3a2a1a0)
00 1a4a3 a2a1a0 : LDA addr (load A from address a4a3a2a1a0)

thx

 

[ads_ee]

01 d2d1d0 s2s1s0 : MOV r1, r2 (copy reg s2s1s0 to register d2d1d0)
01 110 s2s1s0 : MOV M, r (copy reg s2s1s0 to memory)
01 d2d1d0 110 : MOV r, M (copy memory contents to register d2d1d0)
01 110 110 : HLT (halt the processor)

All move operations are coded with the op-code of 01. If the op code is followed by the M reg (indirect reg) op-code twice it's interpreted as a halt.

10 000 s2s1s0 : ADD r (add reg s2s1s0 to register A)
10 000 110 : ADD M (add memory contents to register A)
10 010 s2s1s0 : SUB r (subtract reg s2s1s0 from reg A)
10 010 110 : SUB M (subtract memory contents from register A)

Arithmetic is coded as 10. The 000/010 are codes for add/subtract mode respectively.
A has been implied by the 10 op-code.

11 1a4a3 a2a1a0 : STA addr (store A to memory address a4a3a2a1a0)

Store operations to memory are coded with 11.
A is implied by the 11 op-code.

00 1a4a3 a2a1a0 : LDA addr (load A from address a4a3a2a1a0)
00 000 000 : NOP (do not do anything)

Load operations from memory are coded with 00. Unless followed by 000 twice which then means nop.
A is implied by the 00 op-code.

What originally confused me was all the s2s1s0/d2d1d0 stuff that didn't click as representing source_register[2:0] and destination_register[2:0] (corresponding to the register op-codes.

This still doesn't explain the 7 op-codes and only 6 registers being named. Either there is an extra op-code or there is another register name that is still missing.

Regards,
-alan