Delayed output inside process statement

[neocool]

I am trying to understand why I am getting a delayed responce in the following case. One of the components is outputting several signals based on which the code is supposed to set the trigger high or low.

Trigger: process(clk_in, SIG1, SIG2, SIG3)
begin
	if (clk_in'event and clk_in='1') then
	  if (SAMPLE_CLK_OUT_LOCAL='1') then  
	    if (SIG1='1' and SIG2='1' and SIG3='1') then
	      TRIGGER <= '1';
	    else
	      TRIGGER <= '0';                
end if; end if; end if;

I want the trigger to be synchronous with the first occurence of SIG1/2/3 being high. With the code above, this happens only next clk_in clock cycle. Is it due to delays that make clk_in'even not happen the instant the case is occuring?

I have modified the line if (clk_in'event and clk_in='1') then
by erazing 'event condition like that:

if (clk_in='1') then

Is it the correct way to do it?

Thanks

 

[Beetroots]

What is SAMPLE_CLK_OUT_LOCAL?

You're sampling the logical and of sig1,2,3 on the rising edge of clk_in in this code, which you say you don't want to do.

From your description of your requirement you sound as if you want a purely combinational process to generate the trigger (place only sig1,2,3) in the sensitivity list.

 

[ramesh]

Declare the TRIGGER as VARIABLE instead of SIGNAL and then try. Note that this is syncrhonised with rising edge of the clock as per your code.

 

[r_e_m_y]

Hi neocool,

When you are coding vhdl, always keep in mind that your design will be implemented in hardware (for synthesisable design of course).

When your write the following code :

if (SAMPLE_CLK_OUT_LOCAL='1') then
if (SIG1='1' and SIG2='1' and SIG3='1') then
TRIGGER <= '1';
else
TRIGGER <= '0';
end if;

in a clk_in'event and clk_in='1' condition, this means that you want to design a flip flop register. Your code will be synthesised as the logic equation set on the D input of the flip flop named "TRIGGER". The output Q of your flip flop TRIGGER will be set on the next rising edge of the clk_in.

If you want an asynchronous design (no latch, may generate glitches), you can write outside a process :

TRIGGER <= '1' when (SIG1='1' and SIG2='1' and SIG3='1' and SAMPLE_CLK_OUT_LOCAL='1') else '0';

Hope this will help you :wink:

 

[neocool]

Thanks for the replies.

What is SAMPLE_CLK_OUT_LOCAL?

SAMPLE_CLK_OUT_LOCAL is like a bit clock. I want my samples of data be read on clk_in when SAMPLE_CLK_OUT_LOCAL is high (the last one is twice slower than clk_in).

The flip-flop information is useful. Is there a way though to make my design synchronous and not delayed by one clock cycle? From the test bench it looks like sig1/2/3 go high at the same instant as clk_in and SAMPLE_CLK_OUT_LOCAL go high.
Is the following correct: The flip-flop is created during place and route process. During the run-time, when the process is executed, the logical expression at D input is producing the result, which is going to be seen at Q output only on the next clock cycle. One the next clock cycle because the flip-flop is created to react on rising edge of clk_in. Also, the value at D can change as many times as there is a number of changes in signals in sensitivity list because the block (if (sig1='1' and sig2='1' and..) ) is a combinational block. Does it sound ok? Please correct me if I am wrong anywhere in between the lines or if I am missing out something.


Thank you

 

[r_e_m_y]

whooo

hard to check if all sounds ok, but it seems good.
just one remark : after synthesis, even if a signal is not in the sensivity list, the D input of the flip flop will change if one of the signals used in the combinatory bloc changes.
That means the D input can be not stable for a time ... but it should be at the clk rising edge.

 

[ashishjindal76]

remove all the atribute from the process atribute list except the clock. then try

ashish