delay value in verilog on Left hand side or Right hand side

raviram80 · Dec 24, 2009

Hi All,

I wanted to know the differences between the following verilog constructs

1. X = #5 Y;

2. #5 X = Y;

3. X <= #5 Y;

4. #5 X <= Y;

Please let me know

Thanks,

Syswip · Dec 25, 2009

Re: delay value in verilog on Left hand side or Right hand s

Hi raviram80,

You will find detailed explanation here:

**broken link removed**

Bests,
Tiksan
http://syswip.com/

delay value in verilog on Left hand side or Right hand side

raviram80

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Syswip

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delay value in verilog on Left hand side or Right hand side

raviram80

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Syswip

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