[SOLVED] Delay time calculation

Hi guys,

I'm just curious and not able to found the answer in the internet, how to calculate the delay using clock cycles.
I have read that the equation is :

Clock cycles =(time delay) *(clock frequency/4).

how did it come to that equation (divide by 4). Thanks

which processor, FPGA, or other digital IC are you using?
the answer is likely in the data sheet, buried in how the device handles the clock

I'm using Altera DE10-Lite FPGA Development board. I can't find the specs where I'm supposed to know the relationship between clock frequency, cycles and delay. It have 2 50MHz clocks that I'm using.

Here are the product files:
View attachment m10_handbook.pdf
View attachment m10_datasheet.pdf
View attachment DE10-Lite_User_Manual.pdf

i looked in all three docs you posted and did not find what you're asking about.
where did you find

Clock cycles =(time delay) *(clock frequency/4).


see "Fine Resolution Phase Shift" page 166 of handbook
see "PLL outputs" page 155
see "Figure 6-1: PLL Output Clock Frequency" page 212

chandlerbing65nm said:

I'm using Altera DE10-Lite FPGA Development board. I can't find the specs where I'm supposed to know the relationship between clock frequency, cycles and delay. It have 2 50MHz clocks that I'm using.

Here are the product files:
View attachment 158399
View attachment 158398
View attachment 158397

Click to expand...

I don't get what your issue is exactly (which is why I ignored your first post).

A clock has a frequency, in your case it is 50 MHz. That clock therefore has a clock period of 20 ns between each rising edge, i.e. 1/(50 MHz) = 20e-9. Therefore 1 clock cycle is 20 ns of delay.

If you want to have 500 ns of delay then you have 500 ns/20 ns = 25 clock cycles of the 50 MHz clock will create that much delay.


I have no idea where that equation you showed "Clock cycles =(time delay) *(clock frequency/4)." came from but it requires the clock to be 1/4 of the 50 MHz, i.e. 12.5 MHz.

Perhaps there is a built-in clock prescaler (like, to make
a 4-phase field from a 50MHz main clock)?

Hi,

If you want to have 500 ns of delay then you have 500 ns/20 ns = 25 clock cycles of the 50 MHz clock will create that much delay.

I have no idea where that equation you showed "Clock cycles =(time delay) *(clock frequency/4)." came from but it requires the clock to be 1/4 of the 50 MHz, i.e. 12.5 MHz.

Click to expand...

In my eyes there is no clock divider .... indeed I expect a clock multiplier. (PLL)
Clock cycles =(time delay) *(clock frequency/4).
If you replace with the values of your post:
Clock cycles = 25
Time delay = 500ns
Clock frequency = 12.5MHz
Then the formula is not correct
But if you replace with: clock frequency = 200MHz
Then the formula is correct.

Klaus

KlausST said:

Hi,


In my eyes there is no clock divider .... indeed I expect a clock multiplier. (PLL)
Clock cycles =(time delay) *(clock frequency/4).
If you replace with the values of your post:
Clock cycles = 25
Time delay = 500ns
Clock frequency = 12.5MHz
Then the formula is not correct
But if you replace with: clock frequency = 200MHz
Then the formula is correct.

Klaus

Click to expand...

My oops, good catch.