spec07
Junior Member level 2
Hi,
Am I using the correct way if testing the DLL?
1. Set 1 input pulse for clock reference at phase detector input.
2. Set 1 input pulse for clock in with a delay at VCDL input.
Results:
If the DLL is working properly, the clock reference from the phase detector input and clock out from the output of the VCDL would be able to align (lock) after xxx cycles.
Did I get the testing method and the working principle of the DLL correct?
Please advice. Thank you.
Am I using the correct way if testing the DLL?
1. Set 1 input pulse for clock reference at phase detector input.
2. Set 1 input pulse for clock in with a delay at VCDL input.
Results:
If the DLL is working properly, the clock reference from the phase detector input and clock out from the output of the VCDL would be able to align (lock) after xxx cycles.
Did I get the testing method and the working principle of the DLL correct?
Please advice. Thank you.