Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

delay linearization of multi stage cell

Status
Not open for further replies.

yogi.uniyara@gmail.com

Newbie level 3
Joined
Oct 9, 2010
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,310
hiiiiii,
i having inverter followed by transmission gate, having a linear delay between input an doutput w. r.t input transition time. can u please tell me the reason for that. also, can someone tell me the reasons why generally,delay is linear function of load and transition time
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top