Delay in VHDL code for Xilinx ML 401

macpak · Mar 20, 2007

Hello ,
I have a problem , I try to write vhdl code and i need a delay , it means that i have to
set the signal to '0' , wait some time and then change the state to '1' . And I dont know how to make that delay. I tried to use wait statement but it doesn't work(The compiler says that synthesis doesn't support this kind of statement). I need a delay about a few microseconds. Does anybody know how to resolve it ??

salma ali bakr · Mar 20, 2007

xilinx ml401

make a counter
and load it with any number u want (according to ur clock frequency and the delay u want)
and then make it decrement
and when it reaches zero, then it means times is up and u can proceed with anything after that

echo47 · Mar 21, 2007

ml401

That's correct. Use a high-speed clock and a counter.

Synthesis tools generally don't support delay statements because an FPGA usually doesn't include any predictable delay elements.

Delay in VHDL code for Xilinx ML 401

macpak

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salma ali bakr

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echo47

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Delay in VHDL code for Xilinx ML 401

macpak

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salma ali bakr

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