quiet83
Newbie level 6

Now in my design, the clock signal is generated by a OR gate.
There will be a problem when I do the post-synthesis simulation, because the delay of that cell is too large.
How can I solve this problem?
I have already set the input clock signal as ideal network, and it seems it doesn't work.
Thanks.
There will be a problem when I do the post-synthesis simulation, because the delay of that cell is too large.
How can I solve this problem?
I have already set the input clock signal as ideal network, and it seems it doesn't work.
Thanks.