delay in clock cells for postsynthesis simulation

[quiet83]

Now in my design, the clock signal is generated by a OR gate.
There will be a problem when I do the post-synthesis simulation, because the delay of that cell is too large.
How can I solve this problem?
I have already set the input clock signal as ideal network, and it seems it doesn't work.
Thanks.

 

[Kuxx]

Big delay on the clock gating cell is the result of a big output capacitive load at this cell. You need to use the buffers (repeaters) in the clock path to reduce capacitive load at the first cells in path and decrease delay. This problem can be solved at the layout generation stage by synthesizing clock tree with needed buffers and inverters. But if you want to simulate your circuit at post-synthsesis stage try to resynthesize your RTL with "set_dont_touch_network" attribute on the clock gating port in DC or "preserve" attribute in RC.

Regards,
Kuxx.

 

[quiet83]

I have tried both "set_ideal_network" and "set_dont_touch_network". I can also see the large delay in the sdf file after synthesis.
Does it mean i can't do the post-synthesis simulation, but only post-layout simulation after I finish the layout?

 

[George_P]

I have tired both "set_ideal_network" and "set_dont_touch_network". I can also see the largy delay in the sdf file after synthesis.
Does it mean i can't do the post-synthesis simulation, but only post-layout simulation after I finish the layout?

Hi,

I am having the same problem, the post synthesis SDF defines a huge delay (~50 clk cycles) at root buffer of the clk tree. This leads to timing violations and failure of gate-level simulations.

If you found a solution to this problem, please share it in the forum.

Regards,
George

 

[quiet83]

Hi,

I am having the same problem, the post synthesis SDF defines a huge delay (~50 clk cycles) at root buffer of the clk tree. This leads to timing violations and failure of gate-level simulations.

If you found a solution to this problem, please share it in the forum.

Regards,
George

Hi,

In case of simulation, I just manually changed the value to a very small one in the sdf file and since it will be optimized in the back end phase.

 

[sam536]

can u check the write_sdf command. Is it used SDF 2.0 or 3.0 ..Some of the variables need to control .

Thanks Sam

 

[nature0303]

when you define that network as clock, i think DC regard it as ideal_network by default,so it will no add buffer tree to that network,and if this clock will drive lots of registers, it needs large gates.
i think the delay will be reduced after P&R.If you do want to see the result after DC，you can set_min_delay of that gate,but it may not works well.

 

[Rama krishna k]

the delay of this cell can be decrease in P&R flow.
and i think cell delays in DC is not real and will not correlate with the delays after P&R.

and also check the tran and cap values to that cell, and lib delays.

thanks
Rama Krishna