Delay circuit that can delay the input signal 1 clock period

[rficdesigner]

Dear all,

I face this problem.
It is required the input signal is delay 1 clock period. (see attached file)
I found a solution that uses 2 master-slave D flip-flops.
However, it is not effect (use alot of components), I think.

Do you have any solution please share.
Thanks alot.

 

[mandar_mahajan]

Re: Delay circuit that can delay the input signal 1 clock pe

If u r doing this using controller, use no operation instruction for the delay u want.

 

[rficdesigner]

Thank anyway man; however, I have to implement in CMOS IC design.

 

[AdvaRes]

Re: Delay circuit that can delay the input signal 1 clock pe

Thank anyway man; however, I have to implement in CMOS IC design.

Simply use one flip flop. You can design it using few transistors.

 

[rficdesigner]

Re: Delay circuit that can delay the input signal 1 clock pe

I have to use 2 Master-slave D flip-flops.
The schematic for 1 MS D FF is as attached file.
So it is not effective.
Could you please share ur schematic.

Thank you.

 

[dick_freebird]

You might use the two FFs but clocked antiphase.
Two with the same phase, can have a delay from
1.0xxx to 1.9xxx periods, if the input signal is not
strictly synchronous.

 

[rficdesigner]

Please share your solution that is more effective than using 2 D-FFs.
Thanks you.

 

[Colbhaidh]

Re: Delay circuit that can delay the input signal 1 clock pe

If this is to be implemented inside an IC and assuming the following
(a) Clock is of the order of MHz
(b) This is a really good Foundry process
then..........
Feed the clock into a non overlapping clock generator that generates two non overlapping phases. This can be done with two NOR gates and 3 or 5 or 7, .... invertors. The number of invertors determining the off period between non overlapping phases.

Now feed INPUT into two tri-state invertors in series and connect the enable of the 1st invertor to the leading phase and the second invertor enable to the trailing phase.
INPUT will pass through invertor 1 on the 1st phase charging the gates of the 2nd invertor which is currently tri-state. On clk phase 2, inveror 1 is tri-state but its input capacitors are still connected to INPUT. The output of invertor 2 will be INPUT delayed by one clock period.

This is the same as a dynamic RAM using the input capacitance of the tri-state invertors as the holding cell. So long as clock is running, then what ever appears on the INPUT will be delayed 1 clock cycle from the output. Add more tri-state invertors for longer delays.
Now since the input capacitors of the invertors are small and there will be leakage, the clock eriod must be fast enough to ensure the charge does not leak away. On a good CMOS process this should be in the order of 0.1 seconds, but best not to push it that far.

 

[rficdesigner]

To Colbhaidh,
Thank for your reply.
Could you draw the block diagram of your idea pls.
It is easier for us to understand.

 

[Colbhaidh]

Re: Delay circuit that can delay the input signal 1 clock pe

See attached.