Definition of STatic Phase Error in a PLL charge pump

[ashishjain_1000]

pll static phase error definition

Hello,

I have a question.Static phase error spec makes sense only in the PLL locked condition i.e CP output voltage in locked condition or should it be checked @ 0 and Max CP output voltage?Please comment in this regard...

Regards,
Ashish.

 

[layes2]

only when the pll is locked

 

[electron1999]

Only in locked state! and Actually ABSOLUTELY NEEDED to keep on because this ERROR is what excites the VCO input...