define FPGA IO Pad direction?

[quan228228]

fpga io pad

when i run FPGA. i set a pad in FPGA top file like following.

IOBUF_LVCMOS33_F_8 PAD_ARST (.T(pad_arst_oen ),.I(arst_out ), .IO(ARST ), .O(arst_in ));
The pad " PAD_ARST" I/O direciton is bidirection.

When i open the ucf file with xilinx PACE tool( i use xilinx FPGA), i found the pad " PAD_ARST" is input.

I want to know why the pad direciton is changed to input pad. And could you tell me how to define PAD I/O direciton ?

Thanks!

David

 

[banjo]

how to define io in ucf

Welcome to compiler optimization. The Xilinx tools have determined that no active logic drives your "PAD_ARST" and therefore it downgraded it to an input only. Finding the issue can be a challenge, since the tools only list the output was removed and do not list the exact point in the upstream logic where the signal is either not driven or driven to a constant logic level.

Start combing through the Translation reports and the PAR reports for removed logic. This should point you in the right direction.

 

[quan228228]

to banjo:

Thanks for your instruciton. i am trying.

David