Defination for testcase and test vectors?

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sujittikekar1

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can anybody explain what is testcase, test vectors and testbench in detail?
if block digram is there it will be helpful to understand. and how we apply test vectors to our DUT?
 

sujittikekar1 said:
can anybody explain what is testcase, test vectors and testbench in detail?
if block digram is there it will be helpful to understand. and how we apply test vectors to our DUT?
Click to expand...

This was discussed in this forum recently. Do a search. Basically a TB provides the "infrastructure" and testcases make use of it. FYI - we cover this very extensively in many of our Verification courses such as CFV, Verification Using SystemVerilog, VMM etc. See www.noveldv.com for details

Regards
Ajeetha, CVC
www.noveldv.com
 

1) one case of testbench (such as for test one function of a chip through
configuring testbench) is a testcase.
2) in a testcase, the input and output file or other data is test vectors.

that's all

sujittikekar1 said:
can anybody explain what is testcase, test vectors and testbench in detail?
if block digram is there it will be helpful to understand. and how we apply test vectors to our DUT?
Click to expand...
 

Testbench is the test setup, whereas testcase is a simulation to test a particular functional feature
 

Hi,
To my knowledge test case and testvectors are same, if some other definition exits please let us know as well.

Testbench is a complete environment for any specfic design.

regards
Manmohan
 

Test bench constitutes major portion of Verification environment n test cases r higher leve abstraction stimulus !! ....
 

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