IIRC, it is wire. verilog has `default_nettype <type>. IIRC the default is "wire". you can get `default_nettype logic, at least I think. In 2020, I think it is more common to see `default_nettype none, which forces all regs/wires/logics/etc... to be declared.
A port has a direction, kind, range, datatype, and a name. Everything except the name is optional. SystemVerilog has an elaborate set of implicit defaults for the first port, and subsequent ports. They are somewhat convoluted so SystemVerilog extensors remain 100% backward compatible with Verilog.
If you omit both the kind and datatype, the default kind is wire and default datatype is logic. If you specify the kind, but omit just the datatype, the default datatype is also logic. These rules work for both input and output ports. The following 3 statements are equivalent (same for input ports)
Code Verilog - [expand]
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output x;outputwire x;outputwirelogic x;
There is a difference between input and output ports when you have an explicit datatype but no kind. For input ports, the default kind is wire, but for output ports, the default kind is var (variable).