Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Default type of a Systemverilog port

shaiko

Advanced Member level 5
Joined
Aug 20, 2011
Messages
2,639
Helped
302
Reputation
606
Reaction score
297
Trophy points
1,363
Activity points
18,215
Hello,

Suppose we have an output module port named: x.
We want x to be defined as type "logic".

Do we have to explicitly define it:
Code:
output logic x
Or is it enough to define it as:
Code:
output x
Is x considered to be of "logic" type by default ?
 

vGoodtimes

Advanced Member level 4
Joined
Feb 16, 2015
Messages
1,072
Helped
304
Reputation
608
Reaction score
301
Trophy points
83
Activity points
8,535
IIRC, it is wire. verilog has `default_nettype <type>. IIRC the default is "wire". you can get `default_nettype logic, at least I think. In 2020, I think it is more common to see `default_nettype none, which forces all regs/wires/logics/etc... to be declared.
 
  • Like
Reactions: shaiko

    shaiko

    points: 2
    Helpful Answer Positive Rating

dave_59

Advanced Member level 3
Joined
Dec 15, 2011
Messages
812
Helped
361
Reputation
726
Reaction score
354
Trophy points
1,353
Location
Fremont, CA, USA
Activity points
6,247
A port has a direction, kind, range, datatype, and a name. Everything except the name is optional. SystemVerilog has an elaborate set of implicit defaults for the first port, and subsequent ports. They are somewhat convoluted so SystemVerilog extensors remain 100% backward compatible with Verilog.

If you omit both the kind and datatype, the default kind is wire and default datatype is logic. If you specify the kind, but omit just the datatype, the default datatype is also logic. These rules work for both input and output ports. The following 3 statements are equivalent (same for input ports)

Code Verilog - [expand]
1
2
3
output x; 
output wire x;
output wire logic x;


There is a difference between input and output ports when you have an explicit datatype but no kind. For input ports, the default kind is wire, but for output ports, the default kind is var (variable).

Code Verilog - [expand]
1
2
3
4
5
input logic x;
input wire logix x;
 
output logic x;
output var logic x;


So your first code example is declaring a variable output port, and your second code example is declaring a wire(net) output port.

This is explained further in section 23.2.2.3 Rules for determining port kind, data type, and direction of the IEEE 1800-2017 SystemVerilog LRM.
 
  • Like
Reactions: shaiko

    shaiko

    points: 2
    Helpful Answer Positive Rating
Toggle Sidebar

Part and Inventory Search


Welcome to EDABoard.com

Sponsor

Sponsor

Design Fast


×
Top