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default in case statement

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ASIC_int

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Hi

Suppose in a case statement all case options are provided and a default option is also provided. Will the synthesis tool ignore this default or take care of this default while synthesizing? What about the simulator?
Will the simulator tool ignore this default or take care of this default while synthesizing? What does the verilog IEEE standard says?

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FvM

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You are talking about an "empty" default case?

How should the synthesis tool or simulator take care of it? I expect both to ignore it, but don't see a real problem that's worth to be pursued.
 

ASIC_int

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FVM

Good day. How is life?

I am talking of a case expressions with all case options along with the default is also present. All the case options and also the default will have some values. Neither the default nor any of the case options will be empty. Is it clear now? Please answer the question if the question is clear.

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FvM

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O.K. I see the ambiguity. I meant "empty" in the sense of an empty set, because all cases are covered by explicite case statements. Then the default can't be but ignored, whatever is written in it.
 

ASIC_int

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What I mean all cases are coverd then the default is also covered by a statement. For example if we take a 4:1 mux then the default may be covered by 'a' where 'a' is one of the inputs of the mux.

Will the synthesis and simulator also ignore the default? How do we know this if it is yes. There is nothing available in IEEE spec regarding this.

---------- Post added at 08:01 ---------- Previous post was at 07:53 ----------

What will the simulation do if one of the inputs to this selection line of mux goes unknown ? It will try to remeber the earlier values and so simulator will so it as a latch if the default is ignored by a simulator. But simulator does not work in that way. So I conclude simulator does not ignore the default case. Am I correct? If I am wrong please show how. What abot the synthesis tool?
 

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I agree, that default can play a role in simulation of 'x' or 'z' levels, although the case statement is "full", covering all '0' and '1' combinations of the case expression. But I'm not equipped with any problem where this behaviour would matter. In synthesis, Im sure that the default statement must be ignored for a full case statement (respectively an empty default set).

I'm not aware of additional comments in the IEEE specification relevant for this discussion, but I didn't miss them so far.
 

ASIC_int

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But I'm not equipped with any problem where this behaviour would matter.
I think this behaviour will matter resulting in simulation and synthesis mismatch if we do not provide any default.

I'm not aware of additional comments in the IEEE specification relevant for this discussion, but I didn't miss them so far.
What do you mean bu I do not miss them so far.

Im sure that the default statement must be ignored for a full case statement (respectively an empty default set).
How do you know this that the default statement must be ignored for a full case statement ? From which document did you come to know this? Or, did you do any experiment to confirm it? What are you tring to mean by (respectively an empty default set)? Can you please be more clear?
 

std_match

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How do you know this that the default statement must be ignored for a full case statement ?
You can not change the synthesized result by adding a "default" to a "full" case, since the synthesized hardware can only see '0' and '1'. You should make the simulation as safe as possible by adding a "default" that propagates 'X' to the output signals.

There is a lot about this problem in this document:

http://www.arm.com/files/pdf/Verilog_X_Bugs.pdf
 

ASIC_int

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You can not change the synthesized result by adding a "default" to a "full" case, since the synthesized hardware can only see '0' and '1'.
What do you want to say by the above quote. It was not much clear. Can you please clarify and provide additional things related to the quote.

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std_match

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What do you want to say by the above quote. It was not much clear. Can you please clarify and provide additional things related to the quote.
The synthesis tool will only consider case options with '0' and '1', so if all combinations for '0' and '1' are specified, the default will be ignored (for synthesis).

To avoid simulation mismatch because of the stupid latching behavior in the simulator (the synthesized logic can't do that), the safest thing to do is to add a default that assigns 'X' to all driven signals. That will prevent the latching in simulation.

Why can't the synthesized logic do the latching? Because 'X' is not a value that exists in the physical world.

This is easier in VHDL, where simulation "unknown" is 'X', and synthesis "don't care" is '-'. The synthesis tool can then just refuse to do anything with 'X' and give an error message.

The Verilog handling of 'X' gives a much higher risk for simulation mismatch.
 
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std_match

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I think that my previous posting is a bit confusing since I mix different topics.


1. What is the problem with a Verilog case with no default, but all binary combinations listed?

For synthesis, all possible combinations are covered, so no latches will be generated.
During simulation, 'X' or 'Z' in the input will not match any option, and the outputs will be latched.
To avoid this, a default with 'X' assignments is strongly recommended.

In VHDL, "case" and "selected assignment" must have all combinations covered, including simulation values, so unwanted latches are not so likely. All combinations are normally covered by having a default ("when others").
If you really want latching in VHDL, you can use the keyword "unaffected" (VHDL-93) with "selected assignment" or have a branch without assignment in "case".


2. Why is 'X' so confusing in Verilog?

The 'X' in Verilog normally means "unknown" in simulation and "don't care" in synthesis.
For "casex", 'X' means "wildcard", and it is too easy to write code that synthesize
to something that behaves differently than simulation. Don't use casex for synthesis!

In VHDL, 'X' always means "unknown". You can't do much with 'X' in synthesizable VHDL code. The "don't care" is another value: '-'.
 

ASIC_int

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STD_MATCH

Thanks for clarify many issues and double reply. Though many things are clear , one questions is not still clear. That question is : What do u want to mean by "The synthesis tool will only consider case options with '0' and '1', so if all combinations for '0' and '1' are specified, the default will be ignored (for synthesis)"?

I repeat another question which is not still answered clearly:

How do you know/conclude that the default statement must be ignored for a full case statement ? Have u conducted any experiment or have you see any valid authenticated document?
 

dcreddy1980

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Hi ASIC_int,

if you provide all the case options along with a default option like below example, synthesis tool will ignore the default statement.

module example (input [1:0]sel,input [3:0]din,output reg dout);

always@*
begin
case(sel)
'd0 : dout = din[0];
'd1 : dout = din[1];
'd2 : dout = din[2];
'd3 : dout = din[3];
default : dout = din[0];
endcase
end

endmodule


To explain in boolean equation :

sel_0 = sel[0];
sel_1 = sel[1];
sel_0_bar = ~sel[0];
sel_1_bar = ~sel[1];
din_0 = din[0];
din_1 = din[1];
din_2 = din[2];
din_3 = din[3];

dout = (sel_0_bar*sel_1_bar*din_0) + (sel_0*sel_1_bar*din_1) + (sel_0_bar*sel_1*din_2) + (sel_0*sel_1*din_3)

Any synthesis tool should have above equation represented in circuit. If you are using Xilinx synthesis tool, you see the boolean equation along with the circuit.
 

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STD_MATCH

Thanks for clarify many issues and double reply. Though many things are clear , one questions is not still clear. That question is : What do u want to mean by "The synthesis tool will only consider case options with '0' and '1', so if all combinations for '0' and '1' are specified, the default will be ignored (for synthesis)"?

I repeat another question which is not still answered clearly:

How do you know/conclude that the default statement must be ignored for a full case statement ? Have u conducted any experiment or have you see any valid authenticated document?
The key here is the 'X' value. In simulation, 'X' is a value by itself. It is not '0' or '1', it is something else, the special value "unknown". In the real world (synthesis result) the situation is completely different. The value 'X' (=unknown) does not exist, there are only '0' and '1'. If you use 'X' for synthesis, e.g. assign 'X' to a signal, it means something else: "don't care", which is different from the simulation 'X'. "don't care" can not be separated from '0' and '1', it is '0' or '1' but you leave the decision to the synthesis tool. As I mentioned earlier, it is less confusing in VHDL where "don't care" use another symbol ('-').

If you have a 4 to 1 multiplexer controlled by 2 signals, there are only 4 combinations in the "real world", and the synthesis tool will only generate logic to decode these, because there are no other possible combinations.
Since we have an additional signal value 'X' in simulation, there are more combinations. To be safe in simulation, you should have a default which catches the combinations with 'X' in the input signals, and assign 'X' to the output signals. By doing this, you increase the probability that a (probably unwanted) 'X' in the input signals will propagate to an output signal that you will observe during simulation.
 
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