ASIC_int
Advanced Member level 4

Hi
Suppose in a case statement all case options are provided and a default option is also provided. Will the synthesis tool ignore this default or take care of this default while synthesizing? What about the simulator?
Will the simulator tool ignore this default or take care of this default while synthesizing? What does the verilog IEEE standard says?
Regards
Suppose in a case statement all case options are provided and a default option is also provided. Will the synthesis tool ignore this default or take care of this default while synthesizing? What about the simulator?
Will the simulator tool ignore this default or take care of this default while synthesizing? What does the verilog IEEE standard says?
Regards