Deep Nwell process in cadence 65nm (nmos_rf_6t)

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Ali263

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Dear all I am looking for doing triple well layout for an amplifier. I am using nmos_rf_6t . Though it seems easy for layout but but since there is a restrictions on Lenght and width so i had to use to use MULTIPLE Factor. For multiple factor 3, i get 3 segments for one nmos and each is kept in a separate deep nwell.
I was wondering if its right approach that each segment is placed in a separate deep n well or should i h connect all of them or can use one for them?

In picture M0, M1 has three multiple ,each with 30 fingers. M0 and M1 are also noted in layout
 

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No, all three of them should be in the same well.
 

"multiplier" may instantiate multiple devices, there
should be a "nf" or "m" property alongside w and l
in the PCell that makes multiple fingers in the same
body (at least, this has been the case in every PDK
I have encountered). Be sure you didn't pick the
mosaic / arrayed instance property by mistake?
 

Can you comment fro the screenshot below if you can find m or nf ? what is mosaic/ arrayed?
 

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From this fill-form I would expect a FET
with 72 gate stripes (Number of Fingers)
all in a single (multiplier) body/well.

You indicate originally that you had to
set multiplier to 3 so getting three wells
apiece makes sense.

It's common to have upper bounds on
device size as well as lower. My advice
is to not worry about whether it's 72x1
or 24x3 (especially since it's out of your
hands) and update your schematic to
reflect the layout as-constrained, and
another turn around the track.
 

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