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Deep n well for BJT of a BGR??

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jt_rf

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bjt n well

Hi,

I want to put BJT in DNW like i have done for other mos transistors. It is Vertical PNP type BJT.

the moment i put the BJT inside the DNW, the transistor is not detected in LVS run.

what is the solution for this??

Did anybody face the same problem?? how did you solve it??

thanks in advance.

regards,
JT.
 

what technology process are you working on?

As far as i know if the lateral PNP BJT has it's own NWell layer it will be touching to the DNW layer...which mean it will be shorted.

cheers
 

Buddy...I don't know we can put our BJT's into DNW as our own...

As per my knowledge, we will get BJT's from foundry itself and...one more thing why your LVS is not passing is.....in LVS when we are defining a device we will define that by using the interacting layers...

If we don't follow the exact device tabel....obviously OUR LVS woldn't pass...I mean it wouldn't recognize...!!!
 

You must change LVS command file by yourself.
Please refer to Calibre Manual.
 

hi,

It is a late reply but i thought i will throw some light on it .
you cannot put BJT within a deep nwell.it properties would change if done so and hence it does not get detected.
Solution
1.If the isolation required is substrate isolation thenuse a marker layer to avoid soft check.
2.If the isolation required is noise isolation then run a Deep nwell path along with nwell path around the bjt.
 

Hi,
I think, your BJT Nwell and DeepNWELL are getting shorted. That's why the device is not getting recognised.
Can you tell us the purpose, why are putting it under Deepnwell,?
based on that, we can see how to go forward..
 

Hi

I agree that it is better to firstly make sure if your BJT can be lacated in DNW. In some technology, e.g. IBM SiGe, it is real that BJT is in DNW. Actually DWN is used to form an isolated p-type substrate.

If it is sure that your structure is right, i suggest to check the LVS script. It can only work right when every necessary defined layers are all there in your layout.
 

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