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Debug saveform sampling at 4kHz

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Aussie Susan

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(I posted this in the Xilinx user forum nearly a week ago and have not received any response. Posting here as I'm sure there must be a way... Environment is Vivado 2022.1, programming in Verilog (where applicable) and using a Basys3 board that has a Artix-7 FPGA (XC7A35T-ICPG236C). Susan )


I have an ADC set up that samples at 1kHz that feeds a low pass filter which then sends the samples out via a UART. I think this is working OK but what I really want to look at are the waveforms out of the ADC and the filter.

Using the debug wizard I can add a debug core but the sampling clock wants to run at 100MHz (the overall system clock) which means that I can trigger the debugger to start sampling OK but the sampled data (from the ADC and the filter) are all a single value. This is because I'm taking (say) 8K samples at 100MHz where I really want to take the samples at (say) 4kHz so can see the overall waveform (which is in the 1Hz range).

How do I get the debug core to sample at the much slower rate than the main system clock?

Please note that I'm very much a beginner at this so very clear step-by-step instructions using Vivado 2022.1 will be needed. My board is a Basys3 if that makes a difference.

Susan
 
I haven't used the "debug wizard", I just instantiate an ILA in my code and that way you can define what you want to use as your clock. There's another way, where you open the synthesized design and then add probes to the signals you want to look at, but I've always had problems with this approach.

The only problem with the instantiated ILA is that you have to go back and recompile every time you change something there, but if your project's not that big then it shouldn't be too much of a hardship.

The ILA is created using the IP generator.
 
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    FvM

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OK - more help is going to be required I'm afraid. As I said, I'm a real beginner at this FPGA game.

I created an ILA with 4 probes and a clock, and also created a 'wrapper' around it.
In my top level module I created an instance of the wrapped ILA and also created a 4kHz 'clock' register. I linked my 'clock' to the ILA instance along with the signals that I wanted to monitor and synthesised, implemented and generated the bitstream.

However, when I program the FPGA, I get a message to say "The debug hub core was not detected" and that it was "dropping logic core with cellname : 'design_1_i/ila_0'... frin probes file since it cannot be found on teh programmed device'".

When I look at the schematic I can see the ILA (inside a 'design_1_i' module and also a 'dbg_hub' block but both show the 'clk' port connected to ground - I think they were supposed to be connected to my 'clock' register.
Any idea what I'm doing wrong? What have I done or not done?
Susan
 
Basically an ILA core is connected to a variable number of signals of varying width and has an ila_clock. All the signals connected to ILA, aka the ones you want to debug, MUST belong to the same clock domain as the ila_clock. If you want to monitor signals from other clock domains, you should get in a 2nd or 3rd or 4th ILA.
The ila_clock should also be a free running clock. If you meet these basic requirements, the ILA should also function in hardware.
If you are skeptical, just simulate your design with the ILA. You can see the signals for debug connected to the ILA in simulation which would prove that ILA is instantiated and working correctly.
 

There’s no need for a wrapper, i think you’re making this way more complicated than you have to.

once you’ve created your ILA just instantiate it in the module with the signals your interested in. map the signals (and clock) to the ports of the ILA and you’re done.

And you don’t HAVE to have the signals belong to the same clock domain, just be aware of potential CDC problems with that.
 
I'm missing the keyword "storage qualifier" in the discussion. To sample data at low lower rate than the clock generating the data, you need a clock enable signal originated from the same clock domain, or an expreesion of multiple signals set as storage qualifier in the capture control.
 

I'm missing the keyword "storage qualifier" in the discussion. To sample data at low lower rate than the clock generating the data, you need a clock enable signal originated from the same clock domain, or an expreesion of multiple signals set as storage qualifier in the capture control.
There was no mention of sampling at a lower rate than the data clock. Further, I don't think you can have a "storage qualifier" in the ILA. All you can do is start the data collection based on a trigger condition and it then gathers data at the clock rate until the buffer is full.
 

Hearing about 4 kHz sampling rate, do you expect that the 4 kHz "clock" is a real clock that can be used as ILA clock without timing violations? May be in a beginners design with dubious ripple clock dividers.

I'm not familiar with ILA/Chipscope because I'm mostly designing with Altera/Intel. ILA doc that I reviewed describes the storage qualifier feature. Seriously I can't imagine that the tool lacks this important feature when the competitor offers it since "ages".
 

Xilinx ILA has had qualified storage for a long time, but I don't remember if you have to check some option for getting that feature when the ILA is generated.
 

Xilinx ILA has had qualified storage for a long time, but I don't remember if you have to check some option for getting that feature when the ILA is generated.
Well, I just learned something new. I guess I just never needed this feature. Thanks for opening my eyes, guys.
 

Thank you all for your assistance.
I actually managed to achieve my initial goal with the 'real' code (and without the ILA) by writing out the samples via a UART (which is what I was actually doing - the ILA part was trying to check out the ADC and LPF components).
However I have not given up - the ILA looks to be too useful to not use it. But, as I've said a few times, I'm very much a beginner at this and I need to learn how to develop the apps properly. For this one I started with some Verilog code - actually System Verilog as there were a few 'features' that seemed easier with the extensions provided - and used the ADC and FIR wizards for those components. I couldn't work out how to use the 'design' functionality and it wouldn't let me add the System Verilog code I'd written (apparently it doesn't allow that language variation).
I wanted the output (as numbers) to feed into another of my projects and this was holding me up. Once I'm past this 'road bump' I'm certainly coming back to get this skill under my belt.
Lots to learn... not the least of which is 'terminology'.
(BTW I've realised that I should have been sampling the values from the ADC and LPF at 1kHz and not 4kHz - I was mixing analog/Nyquist sampling up with recording the values from the ADC etc. - but as I couldn't get a clock connected at all, let alone even close to that frequency it didn't really matter. Something for the future)
Susan
 

    FvM

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@Aussie Susan
You must also remember 1 philosophy. One needs to put in an ILA core and observe the debug signals when....
1. A particular functional verification scenario cannot be done through simulation
2. A design is functioning correctly in simulation but not in the FPGA.
 

@dpaul - that is true, but another philosophy is that you need to learn these things before you need them 'for real' and 'in a hurry'.
It is true that I didn't need ILA in this situation but I was treating it as a learning opportunity. However it was taking my aged brain a bit long to do the learning and ultimately the pressure of my other project grew.
Rest assured that becoming familiar with how to program these FPGAs and also how to use the Vivado toolset is near the top of my (ever growing) 'to do' list. I want to be as familiar with implementing my ideas on an FPGA (when appropriate) as I am with computers of all sizes.
Susan
 

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