DDR4 SDRAM

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Musawir

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I am going to design DDR4 SDRAM in verilog.
So the below figure shows the memory subsystem as DDR controller, DDR PHY and DDR DRAM.

I have to design all of these subsystem? From where I will start?
Please alse refer me some good materials related to DDR4 SDRAM. Thanks

 

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Thanks for your kind response.
As I am new to DDR. Now I am just following the DDR4 standard JEDEC spec. I want to implement the whole system as in the above figure. Is it possible first design a memory module and then the memory controller?
 

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Do we need DDR PHY Interface between Memory Controller and DDR DRAM Memory?
 

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Is it possible first design a memory module and then the memory controller?
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A simulation model of the memory in Verilog is always provided by the manufacturer. No need to write that on your own. You can focus on the memory controller part.
 
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Musawir said:
Do we need DDR PHY Interface between Memory Controller and DDR DRAM Memory?
Click to expand...
Generally, yes.
You say you are using JEDEC DDR4 spec as a guide, so you should already have a brief idea which specific functions need to be implemented between logical interface layer implemented in memory controller and I/O buffers.
 
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