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DDR3 memory implementation

promach

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I am trying to work on DDR3 memory implementation.

1. why there are 2 WRITING and READING states ?
2. what are ACTIVATING and REFRESHING states for ?


WF6NB8b.png
 

dpaul

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You can only create a simulation modelof the real hardware. In this link you have posted, go to the right hand side and expand the drop-down 'Simulation Models'. The Verilog RTL is available. Time is of essence, save yourself some effort.
 

promach

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the second set are "Auto Precharge" states ("AP")

once it gets to the end of writing, it does final write + auto-precharge cycle which then lands it cleanly on completion of the write into the precharge state

1) Why A12 has value of "V" ? What does "V" mean ?

XKHp79V.png



2) As for WRITE LEVELING, why "DQS as input, DQ as output" ?

RVTMQ7v.png


3) Could anyone help with explaining how DQSBUFM.v is used in DDR3 implementation ?
 

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ads-ee

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It says in the file that it is a simulation library file. I'm assuming that means it is a simulation ONLY file for a DQSBUFM primitive in the Lattice part you are using. It most certainly would not be synthesized as such a primitive isn't implemented in the FPGA's fabric.
--- Updated ---

You are skipping over your reading of the datasheet it plainly states on page 115 Note 6 that V stands for H or L.

You should really read every word from start to finish of the datasheet before attempting to write code for the part.
 
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matrixofdynamism

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It would be great to know why you are trying to create a hardware model of the DDR3 RAM inside FPGA which is what is being implied here actually.

Vendors often provide simulation library that can be used to in simulation of our system.

Please remember that with high speed interfaces, signal integrity issues can often lead to fault behaviour rather than our memory controller having wrong functionality. Finally I would emphasize that it is best to use the memory controller provided by the FPGA vendor i.e use memory controllers that come with Quartus, Libero e.t.c rather than writing your own. This is because it is a very difficult task to write of these memory controllers.
 

student_078

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I remember there is an analog block sitting between digital logic and the DDR pads. Would promach design and simulate that?
I can design the digital part in ASIC and I am looking for open source study materials on the analog part.
 

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