Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How would one verify an SDRAM controler in simulation

Status
Not open for further replies.

matrixofdynamism

Advanced Member level 2
Joined
Apr 17, 2011
Messages
565
Helped
24
Reputation
48
Reaction score
23
Trophy points
1,298
Activity points
7,369
I am aware that when designing SDRAM controllers, it is important to not just be aware of how the SDRAM works but also be careful about the tight timing requirements. Now with emphasis on this second aspect, how would one go about verifying an SDRAM controller design written in a HDL? Do manufacturers of SDRAMs provide some sort of behavioural model for this purpose?

SDRAMs are common with FPGAs and I know that I can find a ready-made controller for this task. I am asking this question out of curiosity.
 

ads-ee

Super Moderator
Staff member
Joined
Sep 10, 2013
Messages
7,820
Helped
1,811
Reputation
3,632
Reaction score
1,772
Trophy points
1,393
Location
USA
Activity points
59,029
Go to Micron's web site and select the SDRAM from their products and then select a device on that page and you'll find the simulation models.

If SDRAM isn't what you want, then look in the DDR2/3/4 product pages for models of those devices.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top