I am trying to give random inputs to my ddr4 interface in ModelSim tool and getting this error

[Prethiga]

I am not sure how to solve this issue,

`include "ddr_package.sv"

module Rand_Stimulus( DDR_INTERFACE intf,

                      TB_INTERFACE tb_intf);


// Set number of operations to be stored in the queue

parameter num_op = 500;

int read_count = 0;

int write_count = 0;


// Use class for randomization

class Packet;

// Random variables

randc bit [63:0] data_r;

randc bit [31:0] addr_r;

randc bit [1:0] op_r;

// Limit values for op to R/W (01 or 10)

constraint c {op_r >= 2'b01;

          op_r <= 2'b10;}

endclass


//class Gen_Packet

class Gen_Packet;

    rand Packet Packet_array[];

    bit [31:0] addr_queue[$];

    constraint rw {

         foreach (Packet_array)

             Packet_array.op_r dist {READ:= 50, WRITE:= 50};

             }         

    

    function void post_randomize;

         foreach (Packet_array) begin

            if ((i == 0) || (addr_queue.size == 0))

               Packet_array.op_r = WRITE;

            if(Packet_array.op_r == WRITE)

               addr_queue = {Packet_array.addr_r, addr_queue};   

            if ((i > 0) && (Packet_array .op_r   == READ ))

                Packet_array.addr_r   = addr_queue.pop_back;

         end             

    endfunction

    

    function new();

       addr_queue.delete;

       Packet_array = new[num_op];

       foreach (Packet_array)

          Packet_array = new();

    endfunction

    

    //function void print_all() ;

    //foreach (Packet_array)

    //   $display ("addr = %h, data = %h, rw = %h", Packet_array.addr_r,

    //      Packet_array.data_r, Packet_array.op_r);

    //endfunction     

                

endclass

    

// define queue, temp structure union, and class.

input_data_type su[$], Stim_st;

Gen_Packet p;



initial begin

    tb_intf.mrs_update <= 1'b0;

// Generate random fields for num_op operations

    p = new();  // create a packet

    

    assert (p.randomize())

    else $fatal(0, "Gen_Packet::randomize failed");

    //p.print_all();

    

    foreach (p.Packet_array) begin

       Stim_st.data_wr       = p.Packet_array.data_r;

       Stim_st.physical_addr = p.Packet_array.addr_r;

       Stim_st.rw            = p.Packet_array.op_r;

       if (Stim_st.rw == 2'b10)

           write_count ++;

       else

           read_count ++;   

          

        su.push_front(Stim_st);

    end


    wait (tb_intf.rw_proc);

do

   @ (posedge tb_intf.act_cmd ) begin

      tb_intf.data_in = su.pop_back;

    end 

while (su.size != 0);   

end


always_ff @ (intf.clock_t)

begin

    if ((!tb_intf.dev_busy) &&(su.size >0 ) && (tb_intf.next_cmd))

       tb_intf.act_cmd <= 1'b1;

    else   

       tb_intf.act_cmd <= 1'b0;


end


endmodule

ERROR:

# ** Warning: (vsim-8311) System Verilog assertions are supported only in Questasim.
#
run
# ** Fatal: ../src/Rand_Stimulus.sv(67): Unable to check out verification license for randomize() feature.
# Time: 0 ps Iteration: 0 Process: /top/stim/#INITIAL#62(#ublk#41953075#62) File: ../src/Rand_Stimulus.sv
# Fatal error in Module Rand_Stimulus at ../src/Rand_Stimulus.sv line 67
#
# HDL call sequence:
# Stopped at ../src/Rand_Stimulus.sv 67 Module Rand_Stimulus
#

 

[ads-ee]

The warning and failure are clearly identified.

Many of the higher level verification features of Systemverilog are not supported in any version of Modelsim, they are only supported by Questasim (which has a significant up cost associated with it).

assertions aren't supported, but only result in warnings, but the randomize function used in many Systemverilog models you may find will not allow you to simulate with that model in Modelsim. Your options are buy a Questa license, find a different model that isn't SV, or edit the existing model and remove any Systemverilog features that aren't supported, sometimes that requires extensive editing, which means it is usually easier to write your own non-SV model.

 

[Prethiga]

Is there a way we could rewrite the randomize() part of the code as the simulator accepts? Could you suggest a way to do so

 

[ThisIsNotSam]

Is there a way we could rewrite the randomize() part of the code as the simulator accepts? Could you suggest a way to do so

classic verilog has random functions. maybe you can call a funcion that is on a separate .v file and there you generate a random number. I hope it works.