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DDR3 timing analysis-CO-simulation

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Neeru Agarwal

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I am doing SI-CO-Simulation for DDR3 memory interface using hyperlynx 8.0 DDRx timing wizard. During SI in the address and DQS lines i find multithreshold crossing. I would like to know the probable reason for it. Is there any measures to be taken on the layout.
 

techzee

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Hi Neeru,

I have not tried out Co simulation option so am not able to help in that.
@ All: I have similar query in DDRx wizrd spreadsheet. We have an APPNOTE for interpretting wizard results for timing so that is clear. My question is related to SI measurement spreadsheet avaialble.
How are max rise delay, Max slew time calculated as per JEDEC standards we have spec for Slew rate derating(V/ns). While simulating I am encountering violations in max slew time [ps]. Can some one clarify how to interpret the results obtained in SI measurement.

Thanks in advance.
 

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