It would be great to know why you are trying to create a hardware model of the DDR3 RAM inside FPGA which is what is being implied here actually.
Vendors often provide simulation library that can be used to in simulation of our system.
Please remember that with high speed interfaces, signal integrity issues can often lead to fault behaviour rather than our memory controller having wrong functionality. Finally I would emphasize that it is best to use the memory controller provided by the FPGA vendor i.e use memory controllers that come with Quartus, Libero e.t.c rather than writing your own. This is because it is a very difficult task to write of these memory controllers.