[SOLVED] DDR2 in hyperlynx - voltage swing level too high

[allanvv]

What am I doing wrong in my simulation? The voltage levels are too high.

https://i.imgur.com/kCRSE.png

I'm trying to simulate the DDR2 termination schemes according to Altera's external memory handbook.

 

[allanvv]

Oh nevermind, it's supposed to swing around VCC and VSS