DDR2 implementation using xilinx IP core

[acbelgad]

I generated DDR2 Xilinx IP core. In IP core directory, there are two design folders : example design and user design. What is the difference between two.
I used example design as it is unchanged and flashed on ML507 kit but phy_init_done and cal_done signals are not getting high on chipscope.
What may be the problem? Do i need to customize IP core somewhere?

 

[aruipksni]

user design expose the user interface in the tb,
example design has internal generators to create stimulous and test the ddr2.

you must select the wright DDR-2 device, when you create the core, and of course select the wright FPGA device.
then select the right banks to which the ddr2 is connected to the fpga.
the clock rate is an important parameter, so if ddr does not work try to reduce it's clock rate.

 

[acbelgad]

Thanks for replying...i have checked everything and its correct...DDR2 top needs two clocks : sys_clk and idly_clk_200. What is the best way to give these clocks from xilinx ML507 board. This board has 33MHz and 27MHz oscillators.

 

[aruipksni]

Thanks for replying...i have checked everything and its correct...DDR2 top needs two clocks : sys_clk and idly_clk_200. What is the best way to give these clocks from xilinx ML507 board. This board has 33MHz and 27MHz oscillators.

ml507 has 100mhz oscillator used as system clock.

you can have a look also at ML507 reference designs :

https://www.xilinx.com/products/boards/ml507/ml507_10.1_3/reference_designs.htm