DDR2 FPGA interface comparison ?

[kormesii]

What is max data bytes that can be exchanged b/w FPGA & DDR2 memory for spartan3 device ? I.e. max DATA throughtput Bytes/s that cna be stored into DDR2 memory ?
Does someone knows calculator tool for DDR2 memories i.e. clk vs data throughput ?
Tnx !

 

[echo47]

I'm not sure how fast a Spartan-3 can do it, but this Xilinx application note may help you:
"DDR2 SDRAM Memory Interface for Spartan-3 FPGAs"
https://www.xilinx.com/support/documentation/application_notes/xapp454.pdf

That app note refers to XAPP768c (example HDL code), which you can probably get by registration/login with Xilinx. Or maybe you can find it with a Google search.
**broken link removed**

Maximum DDR2 data throughput is easy to calculate by simply multiplying the data bus width by two times the clock frequency. For example, if your DDR2 is 4 bytes wide and your clock is 200 MHz, then your maximum transfer rate is 1600 megabytes per second. Of course, you may lose some speed if you are doing extra refresh cycles or non-optimal timing cycles. A clever controller can use various DDR2 timing techniques to hide overhead cycles.