DDR Controller not available for all families in Quartus

[sebmaster]

Hi,

I was looking at how to interface SDRAM with a PLD and was checking out the prebuilt controllers in the MegaFunction wizard of Quartus and was wondering why they are only available for some logic device families and not the others.

I can understand interfaces like Ethernet or DSP functions requiring PLLs or more LEs than some devices provide but can't really see why a memory controller would, surely its just a (very, very) complex FSM?

Is there a technical reason or is it purely a business one?

 

[FvM]

DDR Controller not available for all families in qu(at)rtus

Which FPGA families are you particularly thinking of?

 

[sebmaster]

Technically its a CPLD since the MAXII was the target in the project I was checking it out on, however i've also noticed on the Altera website they list all the Stratix families but only the Cyclone (not II & III) for the SDR core.

I always thought the Megafunction instantiations were generated VHDL but I suppose it would make sense if they were precompiled.

 

[FvM]

DDR Controller not available for all families in qu(at)rtus

I don't exactly understand what you are talking about. Altera has different DDR IPs (Megafunctions), that in total are covering
all recent FPGA families. Technically, the FPGAs need double-data-rate support and voltage referenced I/O standards for DDR
and also suitable PLL circuits to support the timing calibration of DDR2 and 3. MAX II e.g. has none of these features.

Altera has no SDR Megafunction, but an older SDR reference design and SDR support for NIOS II software processor
(in SOPC builder).

 

[sebmaster]

Hi FvM,

Ok I understand; I was thinking that the Altera IP was similar to the kind of controllers found on OpenCores and so therefore would not require things like specialized outputs or PLLs.

 

[FvM]

DDR Controller not available for all families in qu(at)rtus

As far as I see, also DDR RAM controllers at opencores are using device specific resources and
must be modified to adapt them to other FPGA families.