ddr controller and clocks

[yuvalkesi]

Hi,
I'm writing a ddr1 controller in VHDL (novice @ ddr, but read the spec and the data sheet), and having a hard time understanding the clocks on the system
Please see in this link, page 3:
**broken link removed** (btw, I know Lattice have a controller based on this data sheet, I just want to do it by mysetlf).
I've also attached the picture (1). I don't understand what is the difference between clk and ddr_clk. Let's say we're talking about ddr266 (so the clock freq is 133MHz). Which is the 133MHz? clk, or ddr clk? which is 90deg phase?
I've tried also in altera to find some answers...
Mobile DDR SDRAM Controller Core
See picture attached (2). There's also 2 kinds of clocks (clk and ext_clk). What is the difference between them?
I have 50MHz clock on my board. I understand I need to make a 133MHz clock out of it using a PLL (inside my Cyclone II). But what are all these clock used for?
Thank you!!!
Tom

 

[j_andr]

the specification requires the data source [your controller] align clock slopes in the middle
of data valid window, so the ext. ddr does not have to make any clock shifts;
if a controller logic works with CLK to latch outgoing data to a memory, it has to produce
an EXT_CLK which compensates the internal controller delays;

the controller sends data aligned to a clock slope so to capture them correctly
in an fpga the controller has to shift the clock by ~90 deg;

J.A

 

[yuvalkesi]

Hi,
Thanks for your reply.
So, if I understand correctly, all these clocks have the same frequency (e.g. 133MHz)?
And one of them is 90deg phase aligned?
Tom

 

[j_andr]

controller => DDR

  clk (133)         ___/---\___/---\___/---\___/---\___/----

ext_clk (133)       ___/---\___/---\___/---\___/---\___/----

dqs                 ---HZ----------\___/---\___/---\___/--HZ-

data2ddr            =====HZ==========|D0 |D1 |D2 |D3 |===HZ==

dqs [data strobe] phase aligned to ext_clk, data2ddr centered to dqs

usually clk stores D0 & D1 in 2 output registers and is also used
as a multiplexer switch between D0 & D1


DDR => controller

ext_clk(133)        ___/---\___/---\___/---\___/---\___/----
  
dqs                 ---HZ----------\___/---\___/---\___/--HZ-

data2ctrl           =======HZ==========|D0 |D1 |D2 |D3 |===HZ==
inter. reg           ========================| D1D0  | D3D2  |======

dqs [from ddr] is internally [DLL] shifted to latch D0 on pos. & D1 on neg.
edge then clk_90 on pos edge stores both values in 'single clock rate domain'

J.A