DCap doesnt need any special requirement to arrange it, in fact it is good to fill empty area by decoupling capacitors. for large W, L you should see the aspect ratio, get that confirm from CDE.
We used to break the cap into multiple fingers instead of placing one big cap.Used to have a aspect ratio for W/L.
But i dono the extact reason as to why we did that....
We used to break the cap into multiple fingers instead of placing one big cap.Used to have a aspect ratio for W/L.
But i dono the extact reason as to why we did that....
In order to keep the cap's ESR/ESL (s. dipnirvana's answer above) low enough, it is necessary to have many contacts close to the cap area. The best possible aspect ratio for this is W/L=1 . This is why most PDK libs include a "unit cap", which includes appropriate spice & spectre models, and thus guarantees reasonably accurate sim. results in pre- & postLayout.
If different W/L ratios and/or large W & L values are used, ESR/ESL increases, SRF decreases, and the extracted values will be less accurate. For LF applications and for DC decoupling this still may be perfectly sufficient. I've always used such big caps in (otherwise) empty areas to filter vdd or ref. voltages - as dipak.rf told above. It looks good ;-) - and if you ever need a redesign and more real estate, you can still decrease (or delete) those caps ;-)
I found this in the "Analog Characterization" document of our PDK User guide, but those documents are company confidential, sorry. Hope for your understanding. Still, here's one page from that manual, which could explain it: