Dcap in analog layout unit cap or one big dcap(high w &

[khotkar]

what is dcap in ic designing

Hello friends,

While placing dcap in layout which is better unit cap or one big dcap(high w & L)?
Which is good and why??

 

[erikl]

Re: Dcap in analog layout

What do you mean by dcap? Decoupling cap? If so (no high accuracy needed), you may use high W & L .

 

[khotkar]

Re: Dcap in analog layout

Yeah dcap means decoupling capacitor.
Which type of high accuracy is needed??

Added after 5 minutes:

Is there any limitation for W and L OR we can take any large W/L

 

[erikl]

Re: Dcap in analog layout

Which type of high accuracy is needed??

No high accuracy at all, if it is for decoupling purpose.

Is there any limitation for W and L OR we can take any large W/L

Normally, yes, and even any shape, as long as the DRC allows for. There may be a maximum limit.

 

[dipnirvana]

Re: Dcap in analog layout

W/L of decoupling cap need to be decided , because of ESL and depends on SRF (self resonating frequancy).

In some case , u simply can not put 1206 dcap for higher frequency!!

 

[dipak.rf]

Re: Dcap in analog layout

DCap doesnt need any special requirement to arrange it, in fact it is good to fill empty area by decoupling capacitors. for large W, L you should see the aspect ratio, get that confirm from CDE.

Enjoy...........

 

[sandeep_torgal]

Dcap in analog layout

We used to break the cap into multiple fingers instead of placing one big cap.Used to have a aspect ratio for W/L.
But i dono the extact reason as to why we did that....

 

[erikl]

Re: Dcap in analog layout

We used to break the cap into multiple fingers instead of placing one big cap.Used to have a aspect ratio for W/L.
But i dono the extact reason as to why we did that....

In order to keep the cap's ESR/ESL (s. dipnirvana's answer above) low enough, it is necessary to have many contacts close to the cap area. The best possible aspect ratio for this is W/L=1 . This is why most PDK libs include a "unit cap", which includes appropriate spice & spectre models, and thus guarantees reasonably accurate sim. results in pre- & postLayout.

If different W/L ratios and/or large W & L values are used, ESR/ESL increases, SRF decreases, and the extracted values will be less accurate. For LF applications and for DC decoupling this still may be perfectly sufficient. I've always used such big caps in (otherwise) empty areas to filter vdd or ref. voltages - as dipak.rf told above. It looks good ;-) - and if you ever need a redesign and more real estate, you can still decrease (or delete) those caps ;-)

 

[sandeep_torgal]

Dcap in analog layout

Thanks for the info.. Can you point me to some document regarding this.

 

[dipnirvana]

Re: Dcap in analog layout

Let's see if these helps you

 

[erikl]

Re: Dcap in analog layout

Thanks for the info.. Can you point me to some document regarding this.

I found this in the "Analog Characterization" document of our PDK User guide, but those documents are company confidential, sorry. Hope for your understanding. Still, here's one page from that manual, which could explain it: